1. Field of the Invention
The present invention relates to a method for designing a dummy pattern, an exposure mask, a semiconductor device, a method for manufacturing a semiconductor device, and a storage medium having a dummy pattern design program.
Priority is claimed on Japanese Patent Application No. 2007-162437, filed Jun. 20, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, the depth of focus used in lithographic methods in the development of semiconductor devices has been decreased due to developments in sub-micron technology, and thus it has become difficult to accurately form very small wiring patterns.
With the progress in multilayering techniques, unevenness of the surface of an interlayer insulating film has increased, it has thus become more difficult to form very small wiring patterns on the surface thereof.
To resolve the aforementioned problems, the surface of a semiconductor substrate is planarized using a chemical mechanical polishing (CMP) process.
This CMP process can eliminate unevenness over a narrow range, and at the same time, eliminate unevenness over a wide range, and can efficiently planarize a surface of a semiconductor substrate. Therefore, focusing in lithographic methods also became easy, and very small wiring patterns could be easily formed on a surface of a semiconductor substrate.
However, the CMP process sometimes gave rise to phenomena such as dishing and erosion and degraded the planarity of the surface of a semiconductor substrate onto which the CMP process has been performed.
Dishing and erosion refer to the phenomena of formation of a depression on a semiconductor substrate when the surface of the semiconductor substrate is polished by a pad used in the CMP process.
When an electrode made of copper (Cu), for example, is formed by an isolated wire of large diameter, since this Cu material is softer than the material of the insulating film, Cu tends to be removed easily because of deflection of the pad and the gouging effect of slurry, so the electrode section tends to be shaved off to a large depth locally. This phenomenon is called the dishing phenomenon.
Moreover, when an electrode made of Cu is formed by densely-disposed wires with small diameter, a thin insulating film is formed between the densely-disposed wires, and as a result, the densely-disposed wiring section can be removed easily. This densely-disposed wiring section tends to be removed to a large depth locally, and this phenomenon is called the erosion phenomenon.
The dishing and erosion phenomena form portions of large shaved-off depth and portions of small shaved-off depth on the surface of a semiconductor substrate by the CMP process and cause deterioration in the planarity of the surface of the semiconductor substrate.
Dishing and erosion are phenomena that occur because a substrate surface has isolated wires of large diameter or dense wires of small diameter. Therefore, if the wiring density on a substrate surface is made uniform, these phenomena can be inhibited.
If a pattern (hereafter referred to as a “dummy pattern”) that is formed by the material with the same properties as those of the wiring material is formed in a region free from wiring on a surface of a semiconductor substrate, the wiring density on the surface of the semiconductor substrate can be made uniform, and as a result, the surface of the semiconductor substrate can be shaved off uniformly.
Here, the size and shape of the dummy pattern is important as well as the type of layout to be disposed.
Dummy formation methods for dummy pattern using the CMP process or automatic generating programs for dummy patterns and so on, are disclosed in the Japanese Unexamined Patent Application, First Publication No. H10-293391, the Japanese Unexamined Patent Application, First Publication No. 2001-166452, the Japanese Unexamined Patent Application, First Publication No. 2002-158278, and the Japanese Unexamined Patent Application, First Publication No. 2006-237440.
For instance, the Japanese Unexamined Patent Application, First Publication No. H10-293391, discloses a mask pattern design method for making a mask for forming a dummy pattern by dividing the surface of the semiconductor substrate by a mesh and designing a dummy pattern of optimum density and optimum shape.
The Japanese Unexamined Patent Application, First Publication No. 2001-166452 discloses an automatic design method for a dummy pattern with optimum disposition and optimum density by firstly dividing the dummy pattern into rectangular blocks and processing these blocks sequentially.
Moreover, the Japanese Unexamined Patent Application, First Publication No. 2002-158278 discloses a method for designing a dummy pattern for optimum disposition of a combination of large rectangular dummy patterns and small rectangular dummy patterns to suit the shape and size of the region in which the dummy patterns are formed.
Furthermore, the Japanese Unexamined Patent Application, First Publication No. 2006-237440 discloses a program for calculating optimum density and optimum disposition of a dummy pattern by sequentially replacing adjustment-dummy patterns until the area ratio calculated based on the area of the region on which the dummy patterns are formed and the area of the dummy patterns becomes an optimum value, so that as many dummy patterns as possible are disposed in a region in which dummy patterns are formed.
FIG. 13 is a flowchart illustrating an example of a typical design method for designing a conventional dummy pattern.
The conventional method for designing a dummy pattern includes the four steps mentioned below.    (1) Extracting a chip region and device graphics data    (2) Setting a clearance section and a dummy placement prohibition region    (3) Forming a rectangular dummy pattern (defined by a side of the rectangular dummy pattern and space)    (4) Removing an unnecessary definition section
FIGS. 14 to 17 are plan views illustrating examples of the steps for designing the dummy pattern of an example of a conventional method for designing a dummy pattern based on this flowchart.
FIG. 14 illustrates the first step “Extracting a chip region and device graphics data”. It is a schematic plan view illustrating an example of disposition of a layout of device graphics data sections 202 provided in a chip region 201 on a semiconductor substrate 200.
The device graphics data sections 202 composed of three polygonal shapes are formed on the chip region 201, and portions other than the device graphics data sections 202 is a vacant section 201a. 
FIG. 15 illustrates the second step “Setting a clearance section and a dummy placement prohibition region”. A dummy formation prohibition region 204 is disposed at the top right portion, and a band-shaped clearance section 203 is formed so as to surround each device graphics data section 202.
FIGS. 16A to 16C illustrate the third step “Forming a rectangular dummy pattern (defined by a side of the rectangular dummy pattern and space)”.
As shown in FIG. 16A, a plurality of rectangular dummy patterns 207 is formed in the vacant section 201a. 
Firstly, as shown in FIG. 16C, the size of a rectangular dummy pattern is defined by specifying the “sides” of the rectangular dummy pattern. The layout on which the rectangular dummy patterns are formed is determined by disposing the rectangular dummy patterns with the determined size in the “spaces” of the vacant section 201a without gaps.
FIG. 16B is an enlarged schematic plan view illustrating a center portion in FIG. 16A, while FIG. 16C is a view providing an explanation for defining a rectangular dummy pattern.
As shown in FIG. 16C, the rectangular dummy pattern 207 is formed in a square form defined with one side of length “L”.
A space section 208 whose width is defined as “s” and which surrounds the rectangular dummy pattern 207 is defined.
Next, as shown in FIGS. 16A and 16B, rectangular dummy pattern units 209 defined by the rectangular dummy pattern 207 and the space section 208 are disposed without gap in the vacant section 201a. 
However, the size of the rectangular dummy pattern unit is much larger than the remaining portion in the boundary region of the clearance section 203 or the dummy formation prohibition region 204. Therefore, there is a limitation that a larger rectangular dummy pattern unit cannot be disposed. Thus, vacant regions 201b and 201c on which rectangular dummy patterns cannot be formed, are formed between the clearance section 203 and the rectangular dummy pattern unit 209.
The width of the vacant region 201c is larger than that of the vacant region 201b. 
FIG. 17 illustrates the fourth step “Removing an unnecessary definition section”. In FIG. 17, the clearance section 203 and the dummy formation prohibition region 204 have been removed.
Vacant sections 201f and 201g are formed around the device graphics data sections 202.
The width of the vacant section 201f is specified as the sum of the width of the clearance section 3, width of the vacant section 201b, and width “s” of space section 208 of rectangular dummy pattern unit 209. The width of the vacant section 201g is specified as the sum of the width of the clearance section 3, width of the vacant section 201c, and width “s” of the space section 208 of the rectangular dummy pattern unit 209.
Therefore, the width of the vacant section 201g has been made larger than the width of the vacant section 201f. 
For this reason, uniform pattern density of the surface of the semiconductor substrate could not be obtained, and as a result, dishing or erosion phenomenon could not be suppressed.